Cisco Catalyst Hardware : What is an ASIC ?

Today I am going to talk about the Cisco Catalyst hardware in which you guys heard about the ASIC many time. Now the question is What is the ASIC.

An ASIC is a Application Specific Integrated Circuit is a silicon microchip designed for tasks like bridging or Routing rather than being used for general purpose processing such as a CPU. ASICs are fundamental to how an Ethernet switch works.

ASICs are custom designed for the products they are part of and the solutions they support. In a network switch, an ASIC handles packet recognition, manipulation and L2 / L3 forwarding at extremely high speeds (tens or hundreds of gigabits per second, trending towards terabits per second), while also allowing a rich set of services for the traffic, such as prioritisation (e.g. QoS), accounting (e.g. NetFlow), segmentation (e.g.VRFs and SGTs), traffic filtering and enforcement (e.g. ACLs), path selection (e.g. PBR), and much more.

Fig 1.1- ASICs- Traditional and Programmable

ASIC microchips are measured in nanometers (billionths of a meter). This is the size of the various components, such as transistors, that the ASIC is built from.

A generic CPU is too slow for forwarding traffic in a switch. While a general-purpose CPU may be fast at running random access applications on a laptop or server, manipulating and forwarding network traffic is a different matter. Traffic handling requires constant lookups against large memory tables (e.g. L2 tables for MAC addresses, L3 tables for IP routes, L4 ACLs for Security and QoS, etc)

A generic CPU is too slow for forwarding traffic in a switch. While a general-purpose CPU may be fast at running random access applications on a laptop or server, manipulating and forwarding network traffic is a different matter. Traffic handling requires constant lookups against large memory tables (e.g. L2 tables for MAC addresses, L3 tables for IP routes, L4 ACLs for Security and QoS, etc)

In a generic CPU, all of these tables are held in off—chip memories (not located on the CPU itself) and incur significant performance penalties for frequent memory access. There are also limited data paths and buffers to handle incoming packets (remember,

this is millions or even billions of packets per second). Once packets have been received and queued, the CPU must perform the actual processing functions, finding destination lookups, rewriting packet formats, etc. For these reasons, a CPU is not well-suited for this purpose.

Programmable ASICs

How to get the best of both worlds? How to get the speed we need for multi-gigabit or multi-terabit network devices and also the flexibility to keep pace with new network innovations? These questions led to the concept of programmable ASICs  flexible network microchips designed to adapt to new capabilities as the need emerges, yet still offer the performance networks demand.

Early attempts led to the development of the Field Programmable Gate Array (FPGA). These are essentially simplified ASICs, with reprogrammable logic gates, that can change the original behaviour after manufacturing. 

Although FPGAs do provide a level of flexibility, they are actually very expensive to develop and support. They are not built for any particular task and have little or no onboard memory requiring other chips to provide memory access.

These limitations typically relegate FPGAs to a special purpose role in most network devices. An FPGA may be used to augment the packet forwarding capabilities of a fixed ASIC for that 'one special feature' the fixed chip does not have. 

For example, the Catalyst 4500 Supervisor 8 uses an FPGA to provide VXLAN encapsulation, which the switch ASIC does not support. It is usually too expensive to use FPGAs as the primary forwarding engine for a switch.